1. Field of the Invention
The present invention relates generally to sample and hold circuits, and more specifically to a technique for reducing power consumption in an amplification stage driving a sample and hold circuit while maintaining linearity.
2. Related Art
A sample and hold circuit generally refers to a circuit which samples a signal at corresponding time instances, and stores the samples for further processing. For example, a sample and hold circuit may be used to provide samples of an analog signal to an analog to digital converter (ADC) for conversion to corresponding digital codes.
Frequently, one or more amplification stages are used to provide an amplified version (for example, amplified current and/or voltage) of an input signal to a sample and hold circuit. The signal stored in the sample and hold circuit is provided to subsequent components for further processing.
It is therefore generally desirable that the strengths (charge/voltage) of the samples stored by a sample and hold circuit be linearly proportional to the strengths of the input signal at the corresponding (sampled) time instances.
In a prior technique, an amplifier driving a sample and hold circuit is implemented as a high bandwidth amplifier, consuming higher power, to provide an acceptable level of linearity between the captured samples and the actual input signal strengths at the capture time instances. Such higher power consumption is generally undesirable.
In the drawings, like reference numbers generally indicate identical, functionally similar, and/or structurally similar elements. The drawing in which an element first appears is indicated by the leftmost digit(s) in the corresponding reference number.